Design Trade-offs in the VLSI Implementation of High-Speed Viterbi Decoders and their Application to MLSE in ISI Cancellation
نویسنده
چکیده
A 64 state fully parallel Viterbi decoder in 90 nm CMOS technology compatible with WLAN IEEE 802.11 standard is described. Optimisation of different decoder architectures ranging from radix-2 to radix-16 for reaching multi-Gb/s throughput is performed and trade-offs w.r.t. energy efficiency and area are laid out. Best simulated throughput after placement and routing reaches the value of 3.1Gb/s, corresponding to 1.03 GHz operating frequency. In addition, Viterbi decoder implementing MLSE for ISI cancellation in a POF-based data transmission system is described and implemented in 90nm CMOS technology.
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تاریخ انتشار 2011